ASIC RTL Design/ Staff Engineer

We are seeking a highly skilled and experienced Debug IP Design Engineer/Micro architect to focus on the development of Debug IPs. The ideal candidate will have a strong background in IP design, verification, and delivery, with specific expertise in Core Sight IP design.

About the Role

We are looking for a Debug IP Design Engineer/Micro architect to focus on the development of Debug IPs.

Responsibilities

• Debug IP Design: Focus on the design and development of Core Sight based Debug IPs, ensuring they meet the required specifications and performance standards.
• RTL Design: Utilize your experience in RTL design for complex SoC development using Verilog and/or System Verilog to create efficient and reliable IPs.
• Arm-Based Designs: Apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs.
• Collaboration: Work closely with cross-functional teams, SoC integration & Architecture teams to ensure successful IP delivery within the specified timelines.
• Quality Assurance: Implement rigorous verification processes to ensure the IPs meet all functional and performance requirements.

Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.

Required Skills

• Proven 8+years of experience in RTL design for complex SoC development using Verilog and/or System Verilog.
• Strong understanding of Arm-based designs and/or Arm System Architectures.
• Proficiency in IP design, verification, and delivery, with a focus on Debug IPs.
• Excellent communication and collaboration skills to work effectively with cross-functional teams.

Preferred Skills

• Experience with Core Sight based Debug IP design.
• Strong problem-solving and analytical skills.