ASIC RTL Design Engineer

ASIC RTL Design Engineer

Experience : 3-5 years

Location : Hyderabad

The Verification Methodology and Technology (VMT) team delivers verification methodology and technology for all teams and products. Team member will be working with global teams on providing automation (scripting) and writing testcases for the Static Checks methodologies and technologies covering CDC, Lint, Low-Power, debug and regression.

THE PERSON:

A successful candidate in this position is expected to excel in analytical thinking, problem solving, organizing data, gathering requirements, planning and execution. He/she needs to be a self-starter who collaborates well with team members and customers alike to successfully drive tasks to completion.

KEY RESPONSIBILITIES:

The successful candidate will assume technical responsibilities and hands-on technical role responsible for creating testcases for Static Checks Verification methodologies, review RTL and provide flow automation with Scripting knowledge. The following is a list of key responsibilities that the candidate will assume:

Good knowledge of Verilog, System Verilog; VHDL knowledge is required.

Good knowledge on Scripting PERL, SHELL and TCL is required.

Fundamental knowledge on Static Checks CDC, RDC, LINT and Low Power; UPF

understanding is a plus.

Good debugging skills. Hands-on experience with EDA tools is a plus.

Good understanding of digital electronic design and design verification

processes.

Knowledge of use of AI to automate and debug is a plus.

IDEAL CANDIDATE WILL HAVE:

Hands-on deep technical industry experience with Verilog, testbench and

Scripting.

Good understanding of digital electronic design and design verification

processes

Familiarity with EDA tools for static check verification.

Must possess Strong interpersonal and communication skills and needs to be

a team player

Interested,please share your updated resume to janagaradha.n@acldigital.com