Analog layout engineer
UST
2 - 5 years
Hyderabad
Posted: 27/04/2026
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Job Description
Analog Layout Engineer with 4 years of hands-on experience in TSMC 2nm/3nm advanced nodes. The role involves custom analog/mixed-signal layout development for highperformance CPU/GPU/SoC designs, ensuring DRC/LVS/ERC/EMIR clean layouts. The candidate should have strong expertise in FinFET technologies, analog layout fundamentals (matching, parasitics, noise), and proficiency with Cadence Virtuoso, with close collaboration across design and foundry teams.
They expect the profiles by tomorrow with maximum 30 days' notice period.
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