3–6 years RTL / Memory Modeling Engineer

Location: Bangalore / Remote (India)

About the Role:

We are looking for engineers with strong Verilog/SystemVerilog expertise for RTL and behavioral modeling of advanced memory macros.

Key Responsibilities:

RTL and transactional modeling of memory macros

Develop cycle-accurate behavioral models

Latency/throughput parametrization

Model memory non-idealities including read disturb, write failure probability, retention drift, and soft/hard errors

Support architecture and verification activities

Required Skills:

Strong Verilog/SystemVerilog coding skills

3+ years of relevant industry experience

Experience in RTL or behavioral memory modeling

Understanding of SRAM/memory architecture and timing behavior

Exposure to configurable and scalable model development

Preferred:

Experience with compiler-generated memories or memory subsystems

Verification/debug experience is a plus

Immediate joiners preferred.

Apply at: info@nexticrontechnologies.com